ASMC 2019 - Session 1

Tuesday, May 7 

Session 1 – YIELD ENHANCEMENT / YIELD METHODOLOGIES

Chairs:  Janay Camp, KLA-Tencor; Gary Green, Green Technology Consulting; Jean Wynne, IBM Research
Process characterization techniques for driving yield are critical for successful semiconductor manufacturing. This session covers case studies and new techniques for yield improvements / yield learning and reliability monitoring.

10:05
1.1   A Case Study of Yield Improvement in a FEOL Wet Clean Process​
Reshmi Mitra, Ph.D., Zhiyong Xie, PhD., Samsung Austin Semiconductor

10:30
1.2   Early Testable Addressable Logic (ETAL) Test Structure: Showcasing the Use of an Alternate Logic Yield Learning Test Structure for Technology Development​
Ishtiaq Ahsan, Daniel Greenslit, Toni Laaksonen, Tarl Gordon, Zhigang Song, Yandong Liu, John Masnik, Frank Barth, Shahrukh Khan, Joerg Winkler, Kannan Sekar, Neerja Bawaskar, Steve Crown, Kan Zhang, Martin O’Tool, Bill Evans, Teng-Yin Lin, Mark Lagus, DK Sohn, GLOBALFOUNDRIES

10:55
1.3   Failure Isolation in Ring Oscillator Circuit and Defect Detection in CMOS Technology Research 
Victor Chan, M. Bergendahl, J. Strane, B. Austin, C. Boye, S. Matham, S. Choi, A. Gaul, K.Cheng, A. Greene, D. Lea, T. Levin,  G. Karve, S. Teehan, D. Guo, IBM Research

11:20
1.4   A Study of Probe Contact Resistance Impact on Inline Texting with Difference Bond Pad Design in BEOL
Arthur Gasasira, Eswar Ramanathan, Martin Muthee, Jeffrey Riendeau, Michael Hatzistergos, Jay Mody, Qiushi Wang, Petrov Nicolai, Vincent Liao, Jung Tae Hwang, Krom Raymond, Vandana Venkatasubramanian, Colin Bombardier, Shafaat Ahmed, Christa Montgomery, Owen Brown, Lloyd Smith, Alan Cusick, Edwin Soler, Veenadhar Katragadda, Bill Evans, GLOBALFOUNDRIES

11:45
1.5 Complementary Incentives of Yield and Reliability for Ensuring Defect Detections in Wafer-Manufacturing
Lieyi Sheng, Wei Pan, Zdenek Axman, Vilem Bucek, ON Semiconductor

12:15  Networking Lunch