ISS 2019 Abstract: Tim Olson, DECA Technologies

Adaptive Patterning™- Creating a System to Balance Natural Variation

Tim Olson
Founder and CTO, DECA Technologies

Conventional linear thinking drives to eliminate variation in a manufacturing process. While conceptually sound and productive to a point, the unbridled pursuit of zero variation often leads to significant expense with diminishing return on investment. A novel concept called Adaptive Patterning™ has been created which transforms classic design for manufacturability (DFM) into real-time design within manufacturing enabling perfect compensation for every device to balance natural variation.

Within the semiconductor industry, a transformation is underway that’s dissolving classic industry demarcations. A new class of electronic interconnect (EI) is emerging in which wafer foundries are growing into the domain of SATS (Semiconductor Assembly & Test Services) as witnessed by TSMC’s significant InFO™ investments. Similarly, the leading SATS company, ASE, invested the majority of its 2017 capital on wafer level capacity and capability. The blurring of lines is transforming historic ‘packaging’ into EI structures and processes which closely resemble chip making BEOL interconnect processes.

This transformation in EI is being enabled largely by wafer level fan-out (WLFO) technology. One of the greatest obstacles in creating WLFO manufacturing processes is the natural variation of device location within a reconstituted plastic wafer. Rather than fight the natural variation, Deca drew inspiration from video gaming to create a revolutionary capability with Adaptive Patterning™. For the first time in semiconductors, the design process has moved into manufacturing creating real-time device specific interconnect patterns. The motivation, the methodology, the results as applied to Deca’s M-Series™ WLFO and the future promise of the technology will be presented.

KEYWORDS: Adaptive Patterning™, design for manufacturability (DFM), Wafer level fan-out (WLFO), electronic interconnect (EI), semiconductor packaging, BEOL, SATS, foundries, InFO™, M-Series™