3d-systems-summit-Program 2019

 

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3D & Systems Summit ● 28-30 Jan 2019 ● Dresden, Germany

AGENDA

Monday 28, January 2019

 

16:00 Registration
17:00 Welcome
Guido Überreiter, Vice President / Pre & PostFab Operations, GLOBALFOUNDRIES
Laith Altimime, President, SEMI Europe

Session 1: Market Briefing
Chair:           David Butler, EVP and General Manager, SPTS Technologies

17:10

KEYNOTE
Heterointegration – The path to future complex intelligent systems
Prof. Hubert Lakner, Director, Fraunhofer-Institute for Photonic Microsystems IPMS

17:40

Overview of European laser manufacturing industry for semiconductors
Jose Pozo, Director of Technology and Innovation, EPIC – European Photonics Industry Consortium

18:05

Leveraging I4.0 to drive next wave of growth and efficiency in assembly & test operations
Koen De Backer, Partner, McKinsey

18:30

From 2.5D/3D to SiP and FO-WLP: Overview of the latest advanced packaging platforms on the market
Romain Fraux, CEO, System Plus Consulting

19:00 Networking Reception
 
 
 
Tuesday 29, January 2019
 
 
 
08:00
 
Registration and Welcome Coffee
 

Session 2: Heterogeneous Integration & SiP  
Chair:            Franz Schrank, Senior Manager Process R&D, ams AG              


sponsored by  

08:25

 

Opening
Laith Altimime, President, SEMI Europe

08:35 
 
A Word from Our Sponsor  
 

08:40

System integration & packaging innovation for an AI world
Yin Chang, Sr. VP, Sales & Business Development, ASE Group

09:05

3D Heterogeneous Integration technologies enabling System-Technology co-optimization (STCO)
Eric Beyne, imec Fellow, Program Director 3D System Integration, imec

09:30

Advanced Packaging: A Perspective on 2D and 3D Architectures
Ravi Mahajan, Intel Fellow, Co-Director of Pathfinding in Assembly & Packaging Technologies, Intel


09:55

Ralf Schmidt, Manager R&D – Semiconductor, Atotech


Optimized ECD Cu RDL Process with Via Filling Capability for Next Generation Packaging 
Ralf Schmidt, Manager R&D – Semiconductor, Atotech

10:20

 

Coffee Break

sponsored by    

 

Session 3: 3D Integration
Chair:             Jean Michailos, Senior Program Manager, Technology for Optical Sensors, STMicroelectronics


 

11:15

Wafer Bonding Technology:  Application Drivers and Process Development
Dan Smith, 3D Packaging Integration Engineer, GLOBALFOUNDRIES

11:40

Reliability of fine pitch hybrid bonding interconnects
Joris Jourdon, PhD student, STMicroelectronics        

12:05Atomic Diffusion Bonding: Room Temperature Bonding of Wafers for Creating the Future of Electronic and Optical Devices
Takehito Shimatsu, Professor, FRIS, Tohoku University
12:30

Laser-lift-off (LLO) and CONDOx for wafer ultra-thinning process for 3D stacked devices, TSV, eWLB and WLCSP wafers
Christoph Epple, Senior Sales Engineer, DISCO HI-TEC EUROPE

12:55

3D integration for X-ray and particle detectors designed for backside illumination
Hans von Känel, Co-Founder, G-ray

13:20

 

Lunch Break 

 

Session 4: High Performance Interconnect
Chair:            Severine Cheramy, 3D business developer, CEA-Leti            


 

14:30

Chiplet-based partitioning using Smart Interposer for High Performance Computing 3D Integrated Systems
Pascal Vivet, Scientific Advisor, CEA-Leti

14:55

2.5D interposer for photonics
Franz Schrank, Senior Manager Process R&D, ams AG

15:20

Si Photonics and Wafer Level Packaging progresses at VTT suitable for Tb/s communication links
Giovanni Delrosso, Sr. Scientist, Project Manager, VTT Technical Research Centre of Finland           

15:45

Zero energy connection (0eC) - A new way to transfer data
Erez Halahmi, Vice President, 0eC SA

16:10

 

Coffee Break

sponsored by    

 

Session 5: 5G Session
Chair:            Eric Beyne, imec Fellow, Program Director 3D System Integration, imec


 

16:45

KEYNOTE
Heterogeneous Integration – the Future of Packaging

Steffen Kroehnert, Senior Director Technology Development, Business Development Europe, Amkor Technology Holding B.V. Germany

17:15

Electronics Packaging for RF systems
Karlheinz Bock, Director of the Institute for Electronics Packaging (IAVT), TU Dresden 

17:40

2D/3D RF-System-in-Package Solutions
Claus Reitlinger, Senior Staff Manager Advanced Packaging, Qualcomm RFFE

18:05

 

End

18:30

 

Gala Dinner, Pulverturm Dresden

sponsored by    

   
Wednesday 30, January 2019
   
08:30
 
Welcome Coffee
 

Session 6: Panel Level Integration
Chair:              Hugo Pristauz, CTO and Founder, Bluenetics


08:55

Panel Level Packaging – A Platform for 3D System Integration
Tanja Braun, Head of Assembly & Encapsulation Technologies, Fraunhofer IZM

09:20

"Fan-Out System-in-Board" technology enabling RF and processor module and system-level integration
Martin Schrems, Director Strategy & Business Development, AT&S AG

09:45

A Paradigm shift through panel level processing
Garry Pycroft, VP Sales & Marketing, Deca Technologies

10:10

 

Coffee Break

sponsored by    

 

Session 7: Applications
Chair:             Thomas Uhrmann, Head of Business Development, EV Group      


10:45

Reliability challenges and limitations of TCB 3D SiP stacking with more than 16 dies
Victor Vankov, Head of Advanced Packaging Department, Milandr

11:10

Agile Manufacturing of Glass Carriers for Advanced Packaging
Jay Zhang, Business Development Director, Corning Inc.

11:35

Laser Induced Deep Etching of Glass and its Contribution to Heterogeneous Integration
Roman Ostholt, Vice President LIDE, LPKF Laser & Electronics AG
12:00
STT-MRAM in a 3DIC hybrid bonded die stack as a Last Level Cache (LLC) for high performance computing
Donald A. Draper, CEO, ProPrincipia International Associates

12:25

High Performance Packaging Trends for AI
Jan Vardaman, President and Founder, TechSearch

12:50

Trends in Automotive Packaging 2018
Thibault Buisson, Chief Operating Officer, Yole Développement

13:15

 

Closing Remarks

13:20 Lunch Break
   
   
   
POST EVENT: 3D & Systems Summit attendees are also invited to join Symposium Panel Level Packaging 2019. Following the 3D & Systems Summit, the event is organized by Fraunhofer IZM, 30 January 14:00-18:00. To register for the event, please click here. More details are available here.
Wednesday 30, January 2019

Panel Level Packaging Consortium by Fraunhofer IZM 

  


 
 

 

14:00


The FOPLP of Samsung & Beyond Moore
Richard (KwangWook) Bae, Vice President, Samsung Electro-Mechanics Co., Ltd.

 

14:30


How Fine Line Wiring Influences the Cost of Panel Level Packaging (PLP)
Michael Töpper, Business Development, Fraunhofer IZM

15:00

Panel-level Packaging Concepts for OptoelectronicsBA
Dr. Andreas Plößl, TBA, Osram

15:30

Advanced Insulating Film Materials for Fan-out application
Hiroyuki Sakauchi, Ajinomoto

16:00

 

Coffee Break

 

 

16:30


Evatec's all-in-one FanOut process for organic substrates
Roland Rettenmeier, Senior Product Marketing Manager, Evatec

 

17:00


The wet etching and stripping technology for Fan-Out Panel Level Packaging
Yuki Nakata, TBA, Meltex

17:30

The Fan-Out Panel Option: Where Does it Fit?
Jan Vardaman, President and Founder, TechSearch

18:00

 

End

19:00

 

Evening Event “Sophienkeller”

 

 

 
   

  

COMMUNICATION KIT 
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